Integrated circuit fabrication typically involves the deposition of one or more layers of conductive metal on the active circuit region of a semiconductor wafer—i.e., the main interior region on the front side of the wafer which is used for the fabrication of IC devices. Electroplating processes are a common methodology which is used to accomplish such metal layer deposition. For example, typical electroplating applications include, but are not limited to, copper Damascene electrofill, electroplating of tin-silver alloys which are recently finding increased use in wafer level packaging (WLP) applications (see, e.g., U.S. Pat. Pub. No. 2012/0138471, entitled “ELECTROPLATING APPARATUS AND PROCESS FOR WAFER LEVEL PACKAGING,” hereby incorporated by reference in its entirety for all purposes), and copper electrofill of through-silicon vias (TSVs) (see, e.g.: U.S. patent application Ser. No. 12/193,644, filed Aug. 18, 2008, titled “PROCESS FOR THROUGH SILICON VIA FILING,” now U.S. Pat. No. 7,776,741, issued Aug. 17, 2010; and U.S. patent application Ser. No. 12/577,619, filed Oct. 12, 2009, and titled “ELECTROLYTE CONCENTRATION CONTROL SYSTEM FOR HIGH RATE ELECTROPLATING”; each of which is hereby incorporated by reference in its entirety for all purposes).
While the deposition of a layer of conductive metal may be desired within the active circuit region of a semiconductor wafer, such deposition may be undesirable elsewhere, such as the edge bevel region of the wafer—a narrow a region adjacent to the wafer's edge. However, in many IC fabrication processes, before electroplating may be performed, a thin layer of conductive material must first be deposited to serve as a seed for the electroplating operation to follow, and the process commonly used to deposit this seed layer—physical vapor deposition (PVD) via sputtering—can indiscriminately leave conductive metal deposits within the regions of the wafer where they are not desired. Nevertheless, in order to maximize the size of the wafer's active surface region (and thereby to maximize the number of integrated circuits produced per wafer), the seed layer must be sputtered to very near the edge of the semiconductor wafer, and thus it is typically the case that PVD deposited metal not only covers the active surface region, but also coats the entire front edge area outside the active circuit region, as well as the side edge, and to some degree, the backside. Fortunately, after the PVD seed layer is deposited, electrofill of the conductive metal is much easier to control. In some electroplating systems, such control is achieved by employing an electroplating module and electroplating clamshell wafer holder assembly which excludes the electroplating solution from the undesired areas (such as the wafer edge and backside). One example of a plating apparatus that constrains electroplating solution to the wafer active surface is the SABRE™ clamshell electroplating apparatus available from Lam Research Corp., aspects of which are described in U.S. Pat. No. 6,156,167, “CLAMSHELL APPARATUS FOR ELECTROCHEMICALLY TREATING SEMICONDUCTOR WAFERS,” which is hereby incorporated by reference in its entirety for all purposes.
The PVD metal remaining on the wafer edge after electrofill is undesirable for various reasons. One reason is that PVD metal layers are thin and tend to flake off during subsequent handling, thus generating undesirable particles. This can be understood as follows. At the front side edge of the wafer, the wafer surface is beveled. Here the PVD layers are not only thin, but also unevenly deposited. Thus, they do not adhere well. Adhesion of subsequent dielectric layers onto such thin metal is also poor, thus introducing the possibility of even more particle generation. By contrast, the PVD metal on the active interior region of the wafer is simply covered with thick, even electrofill metal and planarized by CMP down to the dielectric. This flat surface, which is mostly dielectric, is then covered with a barrier layer substance such as SiN that both adheres well to the dielectric and aids in the adhesion of subsequent layers.
To address these problems, a post-electrofill processing system may be designed to remove PVD deposited and electroplated metal from an edge bevel region of a semiconductor wafer. Such an edge bevel removal (EBR) operation may be performed in a post-electrofill EBR module and oftentimes involves a metal etch of the wafer edge followed by a rinse and dry. In some embodiments, a post-electrofill EBR module may be a part of an integrated electroplating system that performs electroplating (electrofill), post-electrofill etching, and potentially other operations such as cleaning operations, for example.
The precision of the EBR operation is important, however. In particular, it's important that an EBR operation does not remove too little or too much metal from a wafer's edge bevel region and that the removal operation is done evenly—i.e., in a substantially radially symmetric manner. Too little metal removal in the edge bevel region may fail to cure the problems noted above, whereas metal removal too far radially inward on the wafer may consume valuable surface area which could otherwise serve as additional active circuit region used for chip production. In sum, an effective EBR operation works to remove PVD deposited and electroplated metal from the edge bevel region as thoroughly and as radially symmetrically as possible—and over the radially narrowest region which is sufficient to cure the deficiencies noted above in connection with deposited metal in this region of the wafer.